The present invention relates to a semiconductor integrated circuit device, and particularly to technology that can be effectively utilized for semi-custom LSIs (large scale integrated circuits) such as gate arrays.
Semiconductor integrated circuit devices such as gate arrays are usually produced in small numbers but in a variety of kinds. Therefore, the manufacturers of semiconductor devices offer base chips for gate arrays having a plurality of gates to meet wide demands of the users. In order to realize a circuit demanded by the user on the base chip, the manufacturer forms a plurality of photomasks for fabricating a user's circuit, and forms wirings among the gates on the base chip by using the mask thereby to obtain a gate array demanded by the user. Therefore, a single chip base is used for fabricating a plurality of semiconductor devices having different functions.
In order to further enhance the general applicability of the gate array itself, the present inventors have studied technology to make it possible to select the input or output interface (signal level that can be input and output) of the gate array out of a plurality of input and output interfaces. The input or output interface portion includes a TTL interface and an ECL interface. Further, the ECL interface must be provided in two types; i.e., an interface of 10-K specification of which the output signals vary depending upon the temperature, and an interface of 100-K specification of which the output signals do not vary depending upon the temperature. It was therefore learned that the input and output buffers of the gate array must be so designed as to be capable of coping with the above interfaces.
The present inventors have studied to provide an efficient layout of input and output buffers to impart general applicability to the input and output interfaces and have accomplished the present invention.
A Bi-CMOS circuit used for the gate arrays has been taught in a journal "VLSI DESIGN", August, 1984, pp. 98-100.